A liquid crystal display (LCD) has matching electrodes on front and back planes with a clear to dark changeable fluid between the two planes. As shown in FIGS. 1A and 1B, a conventional numerical LCD 10 has eight elements configured in the shape of the numeral eight followed by a dot. Specifically, LCD 10 has four vertical elements A, B, C, and D; three horizontal elements E, F, and G; and an element H in the shape of a dot. Either static drive (single back plane) or multiplex drive (partitioned back plane) method can be used to drive an LCD, as is understood by those skilled in the art. A convention 1/3 bias, 1/4 duty cycle (4 back plane partitions brought out to 4 terminals) is illustrated in FIGS. 1A and 1B. One skilled in the art, however, will understand that other bias levels and duty cycles may be used by an LCD.
FIG. 1A is the front plane of LCD 10. There are two voltage supply terminal segments S.sub.1 A and S.sub.1 B on the front plane, with each segment connected to four electrodes. Voltage supply terminal segment S.sub.1 A is connected to electrodes A, F, C, and G and voltage supply terminal segment S.sub.1 B is connected to electrodes E, B, D, and H.
FIG. 1B shows the back plane partitions of LCD 10 with voltage terminals BP0, BP1, BP2, and BP3 each connected to a different pair of elements. As one skilled in the art will understand, if LCD 10 were to include additional numerical displays, i.e., additional numeral eight configurations, back plane voltage terminals BP0, BP1, BP2, and BP3 would be common to all the numerical displays.
The fluid between the front plane and back plane is darkened at a particular element when an AC voltage is applied across the electrodes connecting the element. Thus, to darken element F, for example, an AC voltage is applied across the planes at segment S.sub.1 A and back plane terminal BP1. A constant DC voltage applied across the planes, however, will damage LCD 10.
For LCD 10 shown in FIGS. 1A and 1B, an LCD driver 20 supplies multiplexed voltage levels at 1/4 duty cycle in 1/3 voltage increments to the elements on the back plane of LCD 10 via terminals BP0, BP1, BP2, and BP3. By applying the appropriate voltage level, again in 1/3 increments, to the segments on the front plane of LCD 10 via terminals S1A and S1B, LCD driver 20 controls the display on LCD 10.
FIG. 2 is a graph showing the 1/4 duty cycle, 1/3 bias voltage waveforms supplied by LCD driver 20 to LCD 10. As shown in FIG. 2, one complete scan of voltage waveforms is comprised of two frames, where one scan occurs at a desired frequency, such as 40 or 80 Hz. The first frame includes increasing voltage waveforms, while the second frame has complimentary decreasing waveforms. Thus, the voltage level across back plane terminal BP1 and segment S.sub.1 A, at waveform BP1/S1A, has a positive waveform in frame one and a complimentary negative waveform in frame two. Because LCD driver 20 provides voltage levels with 1/4 duty cycle, there are four phases in frame 1 and four phases in frame 2, for a total of eight phases in a complete scan. Consequently, during one complete scan, there is an average AC bias voltage level with a zero average DC voltage level (integrated over all phases of the scan) across each element.
LCD driver 20 with a 1/4 duty cycle changes the voltages on terminals S.sub.1 A, S.sub.1 B, BP0, BP1, BP2, and BP3 such that the elements between these terminals are at bias voltage (.+-.1/3Vcc) for 3/4 of the scan, and at either the "on" voltage (.+-.Vcc) or at the "off" voltage (.+-.1/3Vcc) for the remaining 1/4 of the scan. Thus, as shown in FIG. 2, the junction of terminals BP1 and S.sub.1 A, which is element F as shown in FIGS. 1A and 1B has an "on" voltage level of +Vcc during phase 2 and a complimentary voltage level -Vcc during phase 6, and has a bias voltage level of .+-.1/3Vcc during the remainder of the scan.
FIG. 3 shows a conventional one-third voltage supply circuit 30 connected to a voltage source Vcc. Voltage supply circuit 30 is a voltage divider having resistors of equal resistance producing voltage levels of Vcc, 2/3Vcc, 1/3Vcc, and ground on respective output terminals Vout1, Vout2, Vout3, and Vout4. Resistive elements 40, 50, and 60 of voltage supply circuit 30 generally have equal resistances, such as approximately 1-10 k.OMEGA. (kilo ohms), although the specific resistances used may vary.
Generally, LCDs have a high resistance and capacitance between the front and back plane, e.g., approximately 1 G.OMEGA. (gigaohm) and approximately 100 pf (picofarads), respectively, for each LCD element. Because of the high capacitance between the front plane and the back plane, a large current source is required to quickly change the terminals of LCD 10 from one voltage level to another. Consequently, it is understood that although FIG. 2 shows square waveforms, in fact at each phase transition there is a settling time produced by the resistance and capacitance decay. A fast settling time, such as less than 5 .mu.s for a 40 Hz scan, is desirable to produce an approximate square waveform, which ensures that the average D.C. voltage levels on LCD 10 over a complete scan will be zero. Because the settling time is a function of current, to produce an approximate square waveform, LCD driver 20 uses a voltage supply circuit 30 that consumes a large amount of current, typically 100 .mu.a (microamps).
However, as shown in FIG. 2, the voltage levels on the terminals of LCD 10 change only at the transition of a phase and are held constant during the phase. Because there is a high resistance in LCD 10, maintaining the voltage levels across each element of LCD 10 during a phase requires little current. Consequently, voltage supply circuit 30 unnecessarily consumes a large amount of current during each phase resulting in large power consumption.